搜索资源列表
FIFO64
- FIFO级联，利用verilog语言实现Xilinx FIFO18单元的多个级联，增大FIFO深度。-FIFO cascade, using Verilog Xilinx FIFO18 language to achieve a number of cascade units, increasing the FIFO depth.
generic_fifos
- Generic FIFO for use with both xilinx and altera
hdlc
- HDLC协议的VHDL源码。接收和发送模块，以及所用FIFO的IP核（Xilinx公司）。-The code of HDLC protocol.Receive and transmit module is contained.
fifoi
- 基于Xilinx Vertex2的可综合的2048x10位的读写可控制FIFO模块源代码，深度可控-Based on the Xilinx Vertex2 can be integrated 2048x10-bit read and write can control the FIFO module source code, the depth of controllable
fifo_core
- 经典的FIFO实现源码，里面有三种类型，是xilinx工程师写的，经典-Classic source FIFO implementation, there are three types, are written by xilinx Engineer, classical
ASYNCFIFO
- 异步FIFO的FPGA实现,XILINX FPGA, ISE ,VHDL语言实现-asynchronous fifo
afifo_0916
- 异步FIFO，使用XILINX产品实现，可以通过改参数来重新修改深度和位宽-Asynchronous FIFO, using the XILINX product realization, you can change parameters to re-modify the depth and Width
fifo64x8_tb
- Testbench for Xilinx 64x8 FIFO.
xapp205_fifo_ctl
- XAPP205 Xilinx FIFO Controller VHDL code
FPGA-Prototyping-by-VHDL-Examples---Xilinx-Sparta
- FPGA prototyping by VHDL examples include FIFO,RAM,ROM,filters, registers and others-FPGA prototyping by VHDL examples include FIFO,RAM,ROM,filters, registers and others
mypro_synfifo
- 基于IP核RAM的同步fifo设计，工程使用Xilinx的开发软件ISE-RAM-based synchronization fifo IP core design, engineering, software development using Xilinx ISE
FIFO_exp
- 一个关于如何使用 xilinx FIFO 的经验，非常值得借鉴-a PFF report about how to use FIFO core
based-on-Xilinx-PCIe-Core-DMA
- 1， 支持由板卡发起的DMA操作，既可以将板卡内的数据快速传输到PC，也可以将PC的数据读取到板卡内。DMA的可以通过PCIe的BAR0空间控制。 2， 利用Xilinx LogiCORE Endpoint Block Plus硬核，兼容Virtex 5、Virtex 6、Spartan 6系列。无缝支持PCIe x8、x4、x1速率 。 3， 在板卡的终端是标准的FIFO接口，可以接入各种形式的数据，例如AD采样数据，光纤数据，DA数据。 4， DriverStudio生成的
fifo_config
- This the fifo made fot Xilinx, spartan 3-This is the fifo made fot Xilinx, spartan 3
FIFO
- 这是一个在xilinx下运行的关于FIFO的IP核设计的程序。-This is a run on the FIFO xilinx IP core design process.
FIFO
- 该代码为FIFO代码，编译环境为Quartus/Xilinx,语言为VerilogHDL-The code for the FIFO code, compile environment Quartus/Xilinx, language VerilogHDL
fifo
- 本程序实现简单的fifo传输，并没有加其他的功能，试用芯片xilinx，verilog语言编写-The program implements a simple fifo transmission, and no other added features, try chip xilinx, verilog language
FIFO_TEST
- XILINX FIFO IP核测试程序，已经通过测试，方便可用-XILINX FIFO IPcore testbench
SDRAM-and-FIFO-for-DE1-SoC-master
- Verilog TUTORIAL for beginners. We had earlier published a Verilog tutorial that made use of the Xilinx ISE Simulator.
pg058-blk-mem-gen
- blockram的手册，适合开发者使用是xilinx的(Blockram manual, suitable for developers to use, is Xilinx)